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Module `Hardcaml.Design_rule_checks`Source

Simple circuit analsysis passes for common issues.

val verify_clock_pins : 
  expected_clock_pins:Base.string Base.list ->
  Circuit.t ->
  Base.unit

Raises if there exists a seqential element (register or memory) whose clock input pin is not in expected_clock_pins. Clocks are defined by the name of input clock signals into the circuit.