123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566openArch_declopenRiscv_declmoduletypeRiscv_input=sigvalcall_conv:(register,Arch_utils.empty,Arch_utils.empty,Arch_utils.empty,condt)calling_conventionendmoduleRiscv_core=structtypereg=registertyperegx=Arch_utils.emptytypexreg=Arch_utils.emptytyperflag=Arch_utils.emptytypecond=condttypeasm_op=Riscv_instr_decl.riscv_optypeextra_op=Riscv_extra.riscv_extra_opletatoI=X86_arch_full.atoIriscv_declletasm_e=Riscv_extra.riscv_extraatoIletaparams=Riscv_params.riscv_paramsatoIletknown_implicits=[]letalloc_stack_need_extrasz=not(Riscv_params_core.is_arith_small(Conv.cz_of_zsz))(* Division and remainder have data-dependent latency on typical
implementations, and are explicitly excluded from the Zkt safe list of
the RISC-V specification ("Data-Independent Execution Latency Subset");
see the documentation in proofs/compiler/riscv_instr_decl.v.
Every other instruction is assumed to be constant-time, as on the other
architectures. *)letis_ct_asm_op(o:asm_op)=matchowith|Riscv_instr_decl.DIV|DIVU|REM|REMU->false|_->true(* All of the extra ops compile into CT instructions (no DIV/REM):
SWAP into xor, add_large_imm into lui/addi/add. *)letis_ct_asm_extra(_o:extra_op)=trueendmoduleRiscv(Lowering_params:Riscv_input):Arch_full.Core_archwithtypereg=registerandtyperegx=Arch_utils.emptyandtypexreg=Arch_utils.emptyandtyperflag=Arch_utils.emptyandtypecond=condtandtypeasm_op=Riscv_instr_decl.riscv_opandtypeextra_op=Riscv_extra.riscv_extra_op=structincludeRiscv_coreincludeLowering_paramsletnot_saved_stack=(Riscv_params.riscv_liparamsatoI).lip_not_saved_stackletpp_asm=Pp_riscv.print_progletcallstyle=Arch_full.ByReg{call=SomeRA;return=true}letsp_min_align=Wsize.U8letmax_store_size=Wsize.U32letinternal_call_conv=Riscv_decl.riscv_internal_call_convend