Hardcaml.ScopeSourceScopes control the process of hierarchical circuit generation.
They track a circuit database of instantiated modules, and a scheme for managing the naming of signals within the design.
Control of name generation in a hierarchy of modules. The position of a module within a hierarchy is determined by a path which leads back to the (single) top most parent module. Signal names may be pre-pended with some represtation of that path.
val create :
?flatten_design:Base.Bool.t ->
?naming_scheme:Naming_scheme.t ->
?name:Base.String.t ->
Base.Unit.t ->
tcreate ?flatten_design ?naming_scheme ?name () creates a new scope. If flatten_design is true, then all module instantions are inlined. Names for wires are determiend by naming_scheme.
sub_scope t label returns a new scope with label appended to its hierarchical path
path t returns the Path.t associated with t. This will determine the prefix used when naming modules that are associated with this scope.
circuit_database t returns the circuit database associated with t. Note that circuit databases are shared among sub_scopes.
flatten_design t returns true when HardCaml will inline all module instantiations.
naming_scheme t returns the Naming.t that t was constructed with.
name ?sep t signal string creates a heirarchical name based on the path of t and string. sep, when provided, determines the separator for path components in the heirarchical name (default is $).
Creates a hierarchical name, built with name, and applies it to the signal.
This is typically used as a partial application to construct a new signal naming operator, .e.g:
let (--) = naming scope in
(* ... other code ... *)
let named_signal = some_signal -- "data" in
(* ... more code ... *)